/*
 * =====================================================================================
 * Copyright (C) 2023 Ingenic Semiconductor Co.,Ltd
 * All Rights Reserved
 *
 * Filename     : reg_riscv.h
 * Author       : Keven <keven.ywhan@ingenic.com>
 * Created      : 2024/06/19 14:10
 * Description  :
 *
 * =====================================================================================
 */

#ifndef __REG_RISCV_H__
#define __REG_RISCV_H__

#include "reg_base.h"

#define RISCV_CCSR             (RISCV_BASE + 0x00)    /*!< Core Control Status Register    , RW, 0x000         */
#define RISCV_CRER             (RISCV_BASE + 0x04)    /*!< Core Reset Entry Register       ,RW, 0x004          */
#define RISCV_MBOX_FROM_HOST   (RISCV_BASE + 0x08)    /*!< LEP Mailbox Register From Host  , W, 0x008          */
#define RISCV_MBOX_TO_HOST     (RISCV_BASE + 0x0c)    /*!< LEP Mailbox Register To Host    , W, 0x00c          */
#define RISCV_TIME_L           (RISCV_BASE + 0x10)    /*!< Time Counter Low 32 bit Register, RW, 0x010         */
#define RISCV_TIME_H           (RISCV_BASE + 0x14)    /*!< Time Counter High 32bit Register, RW, 0x014         */
#define RISCV_TIME_CMP_L       (RISCV_BASE + 0x18)    /*!< Time Compare Low 32bit Register ,RW, 0x018          */
#define RISCV_TIME_CMP_H       (RISCV_BASE + 0x1c)    /*!< Time Compare High 32bit Register, RW, 0x01C         */
#define RISCV_IRQ_MASK_L       (RISCV_BASE + 0x20)    /*!< External IRQ Mask Low 32bit Register, W, 0x020      */
#define RISCV_IRQ_MASK_H       (RISCV_BASE + 0x24)    /*!< External IRQ Mask High 32bit Register, W, 0x024     */
#define RISCV_IRQ_PEND_L       (RISCV_BASE + 0x28)    /*!< External IRQ Pending Low 32bit Register, R, 0x028   */
#define RISCV_IRQ_PEND_H       (RISCV_BASE + 0x2c)    /*!< External IRQ Pending High 32bit Register, R, 0x02c  */
#define RISCV_SIP              (RISCV_BASE + 0x30)    /*!< Software Interrupt Pending 32bit Register,RW, 0x030 */

#endif /* __REG_RISCV_H__ */
